Certain pipelines may allow for reads and writes to be issued out of the programming sequence. A pipeline bypass of the write hazard for a previous programming read is a common practice to resolve this issue. However, shared processors and/or direct memory accesses (DMAs) and/or peripheral spaces may have sequential programming requirements that cannot be bypassed.
A write buffer at the end of the pipeline may allow for buffering writes to avoid additional pipeline stalls in the case of memory conflicts. However, additional write buffer hazard detection may be required to ensure reads inside the write buffer are bypassed. A write is held in the write buffer until an access is free, or until there is an overflow, but this may not occur for shared processors and/or direct memory accesses (DMA) and/or peripherals. For level 2 (L2) data cache memory accesses, a level 1 (L1) data cache memory management unit (MMU) may indicate whether memory is volatile or not, so that the memory management unit (MMU) may indicate whether the write is to be buffered. Integration of out-of-order (OOO) programming pipeline bypass and write buffer functionality remains problematic.